Empirical Circuit Model for Output Capacitance Losses in Silicon Carbide Power Devices

Abstract

In recent reports, a variety of power devices, including wide-bandgap transistors, SiC diodes, and Si superjuction MOSFETs, exhibit losses occurring from hysteretic charging and discharging of their output capacitance (C OSS for MOSFETs and C J for Schottky diodes). In many instances and soft-switching power converter applications, these losses are comparable to conduction losses, especially for HF/VHF switching frequencies. Manufacturer SPICE models and datasheets do not report these losses, and are why device power dissipation in simulation significantly contrasts with that in actual converters. However, we propose a viable empirical circuit model that incorporates these losses, with capabilities to integrate into circuit simulation tools such as SPICE. We, in addition, demonstrate the model by comparing device power dissipation in a class-E inverter and class-E rectifier between simulation and implementation.