FPGA-based Dynamic Duty Cycle and Frequency Controller for a Class-E2 DC-DC Converter

Abstract

This paper presents a controller that achieves zero-voltage and zero-dv/dt switching (ZVS and ZVDS) for a class-E2 dc-dc converter under a wide variation in the input and output voltages. One of the major problems in using the class-E topology for dc-dc conversion is that the increased switching loss significantly degrades the efficiency when the voltage condition deviates from the point which the circuit is designed for. The proposed controller modulates the duty cycle and the frequency of the gate driving signal so that ZVS and ZVDS are always achieved under the voltage variation, while regulating the output voltage by on-off control. We demonstrate an FPGA-based prototype controller in conjunction with a 2 MHz isolated class-E2 dc-dc converter that minimizes the efficiency drop due to the switching loss for the input voltage from 80 V to 200 V and the output voltage from 5 V to 20 V.